Playback method, playback control circuit and playback apparatus for a recording medium

ABSTRACT

Stable playback performance is assured and data loss due to out-of-step synchronization is reduced even when playback signal quality deteriorates due to such cause as a recording medium defect. The playback method applies to a recording medium to which data is recorded in block units containing multiple fixed-length frames together with block address information. The data and the block address information are acquired from the recording medium. The recording position of each frame in a block is then predicted from the acquired block address information. Synchronization is then set to the frame level based on the acquired data, and the memory address for storing the acquired data is determined based on the predicted recording position. The acquired data is then stored at the determined memory address.

BACKGROUND OF THE INVENTION

[0001] 1. Technical Field of the Invention

[0002] The present invention relates generally to a method and anapparatus for reproducing information recorded to a recording medium fordigitally recording information. More specifically, the inventionrelates to a method and an apparatus for reproducing data recorded inblock units recorded to a recording medium having prerecorded addressinformation, each block containing a plurality of specific frame unitsassociated with the address information. The invention also relates to aplayback method, a playback control circuit and playback apparatus forreproducing data from a recording medium, such as magnetic recordingmedia and optical discs, to which error-correction coded data isrecorded distributed among plural frames.

[0003] 2. Background Art

[0004] As data transmission technologies have followed a singular pathtowards higher speed and greater capacity with the development of theinformation society, the need for faster, higher capacity recordingmedia for recording and storing this information has also grown.

[0005] Data is generally recorded, reproduced, and managed in blockunits of a specific byte length on recording media for recording digitalinformation. Examples of such recorded data include:

[0006] (1) All types of user data, including digital audio, video, andcomputer data

[0007] (2) Error correcting code (parity code) for detecting orcorrecting data errors during data playback operations

[0008] (3) Redundant data such as data IDs for identifying where data isrecorded. This data is recorded as a coded stream after conversion tomodulated code according to the read/write signal characteristics of therecording medium. A synchronization code is often encoded and theninserted at regular intervals in the modulated code stream and recordedembedded in the modulated code.

[0009] The synchronization code is used to assure correct datasynchronization when reading data. The playback drive reads the data IDafter frame synchronization, detects the recording address identifyingwhere the data is recorded, and then demodulates and corrects for errorsin the required playback data to acquire the original data.

[0010] One method used to record the synchronization code is recording aspecific pattern at the beginning of a data frame of a known unit bytelength. A pattern that does not exist in the modulated code stream isused for the synchronization pattern. The synchronization code is acombination of this specific pattern and a type identifier so that thelocation of the frame in a block can be known by decoding the typeidentifier in a synchronization code for either a single frame or formultiple consecutive frames.

[0011] This is described below using by way of example the physicalformat of DVD (=Digital Versatile Disc) media, a multipurpose opticaldisc medium that is becoming increasingly popular. Run-length limited(RLL) coding in which mark length and space length is limited to therange 3T to 11T (T being the channel bit period) is used for themodulated code stream, and a unique 14T pattern that therefore does notexist in the modulated code stream is used as a synchronization code atthe beginning of the frame. One sector consists of 26 consecutiveframes, each frame containing 2048 bytes of user data. A data IDidentifying the data is assigned to each sector. One block contains 16consecutive sectors, and encoding/decoding the error correcting code isdone by block unit. The frame start synchronization code includes one ofeight predefined type identifiers placed before the unique 14Tsynchronization code pattern. These eight synchronization codes arelabelled SY0, SY1, SY2, SY3, SY4, SY5 SY6, SY7. The first frame in eachsector includes the data ID of the SY0 synchronization code location,and the remaining 25 frames contain one of synchronization codes SY1 toSY7.

[0012] A drive for reading this type of optical disc can thereforedetermine the first frame in a sector by reading synchronization codeSY0, can know where data is recorded by reading the data ID, and can usethis information for search (seek) operations. The frame location withina sector can also be known by correctly reading the type identifiers forthree consecutive frames other than frame SY0.

[0013] Storage media such as recordable optical discs that can bewritten by the user have unique address information prerecorded to thedata recording tracks in a form (such as a different grooveconfiguration) different from that used to record data (such as a phasechange in the recording film). Data is recorded with a link to thepre-recorded address information, and the relationship between therecorded user data and the physical disc location identified by theaddress information is generally predefined. A disc drive that writesdata to such recording media records data with reference to this uniqueaddress information as described in Japanese Patent Laid-OpenPublication No. H11-176081.

[0014] DVD and other optical disc media also typically use Reed-Solomoncoding or other error correcting code to correct errors caused by discdefects or dust or scratches on the disc surface.

[0015] The relationship

d≧2*t+1

[0016] is generally true in an error correcting code where d is theshortest code distance and t is the number of corrections.

[0017] If the location of the error is already known to the errorcorrecting process, erasure correction using information identifying thelocation of a known error, i.e., a erasure pointer, is possible, and thecorrection count can be increased a maximum of two times by applyingerasure correction.

[0018] If the detection correction count is e, then

d≧2*t+e+1

[0019] is true. For example, code with shortest distance d=33 where allerasures are corrected enables correcting a maximum 32 errors (t=0,e=32).

[0020] Erasure correction requires that the locations of the errors areidentifiable, and various methods have been proposed for identifyingwhere errors are located.

[0021] With optical discs and other recording media using a framestructure to record data, error correcting performance is improved bydetecting bit slip from the result of synchronization code detection andidentifying where errors have occurred. The frames recorded to suchmedia are formed by segmenting the error correction coded data intomultiple data frames of a fixed length, converting the data frames tomodulated frame data, and prepending a specific synchronization code tothe beginning of the modulated frame data as described in JapanesePatent Laid-Open Publication No. S63-157372 (page 3, FIG. 3).

[0022] Other methods combine code with a higher error correctioncapability for burst error detection and code with a lower errorcorrection rate and low redundancy rather then rely simply onsynchronization code detection as described in “Optical Disc System forDigital Video Recording”, Narahara Tatsuya and seven others, Part of theJoint International Symposium on Optical Memory and Optical Data Storage1999, July 1999, No. 3864, p. 50, and “Error Modeling and PerformanceAnalysis of Error-Correcting Codes for the Digital Video RecordingSystem”, Narahara Tatsuya and two others, Part of the JointInternational Symposium on Optical Memory and Optical Data Storage 1999,July 1999, No. 3864, p. 340, and Japanese Patent Laid-Open PublicationNo. 2001-515642 (pp. 10-11, FIG. 2). In this case two codewords areformed between synchronization codes, error correction with a highcorrection rate is combined with synchronization code detection, anderasures are identified for erasure correction of the low errorcorrection rate code.

[0023] Methods for improving error correction by locating errors duringerasure error correction of the detection result of synchronizationcode, that is, by generating a erasure pointer, have thus conventionallybeen used.

[0024] A number of problems are left unsolved by the related artdescribed above.

[0025] The first problem is that data playback is synchronized to aspecific pattern contained in a synchronization code that is recordedwith the data, and search (seek) operations depend on reading a data ID.For example, if the synchronization code in the first frame of aparticular sector (synchronization code SY0 with DVD media) cannot beidentified, the data ID cannot be read, and data seek operations are notstable.

[0026] While the location of a particular frame within the sector can bedetermined if synchronization codes can be read from plural consecutiveframes not including the first frame in the sector, synchronization cantake a long time or synchronization may not be possible if the data islow quality.

[0027] It may also not be possible to identify the type ofsynchronization code if data quality is low and synchronization is outof step during demodulation and error correction after the data seek iscompleted and recorded data is read from the addressed location.Furthermore, if synchronization remains out of step for plural frames,it is not possible to recognize frame slipping when it occurs. Evenafter the synchronization codes can be read again after recovering fromthis unsynchronized state, synchronization codes must again be read frommultiple frames in order to determine the frame location, and the dataerror rate can increase.

[0028] The following problems are also presented by relying onsynchronization code detection to generate erasure pointers for erasureerror correction.

[0029] The first problem is that because the circuit block forsynchronization code detection and the circuit block for errorcorrecting using the detection results are different, the results ofsynchronization code detection synchronized to the demodulateddemodulation data must be sent to the error correcting circuit block.

[0030] The second problem is that because the timing for generating thedetection result of synchronization code and the timing for errorcorrection differ, the detection result of synchronization code must bestored until error correction can be applied. Synchronization codedetection also occurs before playback signal demodulation so that framesynchronization can be completed before playback signal demodulation.

[0031] The demodulated data is also typically buffered to DRAM or othermemory device before error correction, and error correction starts afterall frames in the error correcting code block have been stored. Thetiming for generating the detection result of synchronization codetherefore differs from the error correction timing, and detection resultof synchronization codes must be stored until error correction isprocessed.

[0032] A first object of the present invention is therefore to assurestable playback performance and reduce data dropout due to out of stepsynchronization even when playback signal quality deteriorates due to arecording medium defect, for example.

[0033] A second object of the invention is to use the demodulated dataand the corresponding synchronization detection result information forerror correction.

SUMMARY OF THE INVENTION

[0034] A playback method according to the present invention for arecording medium to which data is recorded in block units containingmultiple fixed-length frames together with block address informationcomprises steps of: acquiring the data and the block address informationfrom the recording medium; predicting the recording position of eachframe in a block from the acquired block address information;synchronizing to the frame level based on the acquired data;

[0035] determining the memory address for storing the data acquiredbased on the predicted recording position; and storing the acquired dataat the determined memory address.

[0036] Preferably, this playback also has steps of: determining whethersynchronization at the data frame unit level has been established; anddetecting whether synchronization at the frame unit has been restored ifframe synchronization goes out-of-step. When recovery of framesynchronization is detected, the memory address to which data is storedis determined based on the predicted frame recording position.

[0037] A playback control circuit according to the present invention fora recording medium to which data is recorded in block units containingmultiple fixed-length frames together with block address informationincludes: signal reading means for acquiring the data and the blockaddress information from the recording medium; a recording addresspredicting means for predicting the recording position of each frame ina block from the acquired block address information; synchronizationmeans for synchronizing to the frame level based on the acquired data;memory for storing the data; and control means for determining thememory address for storing the data based on the predicted recordingposition.

[0038] This playback control circuit preferably also has asynchronization detection means for determining whether synchronizationat the data frame unit level has been established, and detecting whethersynchronization at the frame unit has been restored if framesynchronization goes out-of-step. The control means determines thememory address to which data is stored in memory based on the recordingposition predicted by the recording address predicting means when thesynchronization detection means detects recovery of framesynchronization.

[0039] A playback apparatus for according to the present invention for arecording medium to which data is recorded in block units containingmultiple fixed-length frames together with block address informationincludes the playback control circuit above mentioned.

[0040] A further playback method according to the present invention forreproducing data from a recording medium to which is recorded modulatedframe data and a specific synchronization code prepended to thebeginning of the modulated frame data, the modulated frame data beingerror correction coded data segmented into multiple frame data blocks ofa specific length and then modulated, includes steps of: acquiringsignals from the recording medium; acquiring a detection result ofsynchronization code by detecting frame synchronization codes from theacquired signals; correcting frame synchronization based on the acquireddetection result of synchronization code; generating a resultinformation for detection of synchronization code coded according tospecific rules from the detection result of synchronization code;demodulating the modulated frame data for each frame and generatingdemodulated frame data; and adding the result information for detectionof synchronization code for each frame to the corresponding demodulatedframe data.

[0041] This playback method preferably also includes a erasure pointergenerating step for generating a erasure pointer for erasure correctionbased on the demodulated frame data using the corresponding resultinformation for detection of synchronization code; and an errorcorrecting step for erasure correcting error correcting code composedfrom multiple demodulated frame data blocks using the erasure pointersfor the demodulated frame data.

[0042] Further preferably, there is a memory step for storing the resultinformation for detection of synchronization code and correspondingdemodulated frame data in different memory areas with a knowncorrelation therebetween.

[0043] Yet further preferably, the result information for detection ofsynchronization code is coded to differentiate between at least thethree detection results of “normal detection” when the synchronizationcode is detected normally, “undetected” when the synchronization code isnot detected, and “out-of-step synchronization” when a nextsynchronization code is detected at a timing offset from a timingpredicted from the timing of the detection result for the previouslydetected synchronization code.

[0044] Yet further preferably, when the frame synchronization stepcorrects synchronization delay in which a new synchronization code isdetected earlier than the timing predicted from the timing of thedetection result of the previously detected synchronization code, andthe synchronization delay is less than one frame, the memory stepcorrects the memory address of the frame data immediately aftersynchronization delay correction to an address derived by skipping anamount equivalent to the synchronization delay correction, and storesthe frame data to the corrected address.

[0045] Yet further preferably, when the frame synchronization stepcorrects synchronization delay in which a new synchronization code isdetected earlier than the timing predicted from the timing of thepreviously detected synchronization code, and the synchronization delayis greater than or equal to one frame, the memory step corrects thememory address of the result information for detection ofsynchronization code and frame data immediately after synchronizationdelay correction to an address shifted equivalently to the correctionfor the synchronization delay, and then stores the data to the correctedaddress; and the erasure pointer generating step determines that resultinformation for detection of synchronization code that is skipped andnot stored to memory was undetected, and generates a erasure pointerthereto.

[0046] A further playback control circuit according to the presentinvention for reproducing data from a recording medium to which isrecorded modulated frame data and a specific synchronization codeprepended to the beginning of the modulated frame data, the modulatedframe data being error correction coded data segmented into multipleframe data blocks of a specific length and then modulated. The playbackcontrol circuit includes: a frame synchronization means for correctingframe synchronization based on a detection result of synchronizationcode acquired by detecting frame synchronization codes from playbacksignals acquired from the recording medium; a result information fordetection of synchronization code generating means for generating resultinformation for detection of synchronization code coded according tospecific rules from the detection result of synchronization code; ademodulation means for demodulating the modulated frame data for eachframe and generating demodulated frame data; an adding means forprepending result information for detection of synchronization code fora frame to the beginning of the demodulated frame data; memory forstoring the result information for detection of synchronization code anddemodulated frame data; and memory control means for storing the resultinformation for detection of synchronization code and demodulated framedata to memory.

[0047] Further preferably, this playback control circuit also includes:a erasure pointer generating means for generating a erasure pointer forerasure correction using the result information for detection ofsynchronization code; and an error correcting means for erasurecorrecting error correcting code composed from demodulated frame datausing the erasure pointers.

[0048] Yet further preferably, the result information for detection ofsynchronization code is coded to differentiate between at least thethree detection results of “normal detection” when the synchronizationcode is detected normally, “undetected” when the synchronization code isnot detected, and “out-of-step synchronization” when a nextsynchronization code is detected at a timing offset from a timingpredicted from the timing of the detection result for the previouslydetected synchronization code.

[0049] Yet further preferably, when the frame synchronization meanscorrects synchronization delay in which a new synchronization code isdetected earlier than the timing predicted from the timing of thepreviously detected synchronization code, and the synchronization delayis less than one frame, the memory control means corrects the memoryaddress of the frame data immediately after synchronization delaycorrection to an address derived by skipping an amount equivalent to thesynchronization delay correction, and stores the frame data to thecorrected address.

[0050] Yet further preferably, when the frame synchronization meanscorrects synchronization delay in which a new synchronization code isdetected earlier than the timing predicted from the timing of thepreviously detected synchronization code, and the synchronization delayis greater than or equal to one frame, the memory control means correctsthe memory address of the result information for detection ofsynchronization code and frame data immediately after synchronizationdelay correction to an address shifted equivalently to the correctionfor synchronization delay, and then stores the frame data to thecorrected address; and the erasure pointer generating means determinesthat result information for detection of synchronization code correspondto a frame that is skipped and not stored to memory was undetected, andgenerates a erasure pointer thereto.

[0051] Yet further a playback apparatus according to the presentinvention for reproducing data from a recording medium includes theplayback control circuit above mentioned.

[0052] By providing means for predicting the location of recorded datafrom address information prerecorded to the recording medium, theplayback method and apparatus of the present invention can hold framesynchronization more consistently. Frame synchronization can also bequickly restored even when the signal quality of the recorded datadeteriorates temporarily due to a scratch or dust on the recordingmedium.

[0053] Furthermore, by recording demodulated data to buffer memory inframe units, the playback method and apparatus of the present inventioncan quickly correct the address to which data is stored after recoveringfrom out-of-step synchronization. Loss of demodulated data can thereforebe minimized and the effect of error correcting code can be maximizedeven when the quality of the recorded data deteriorates due to repeatedrecording or dust or a scratch on the recording medium. The playbackmethod and apparatus of the present invention are therefore extremelyeffective when applied to a high capacity video disc recorder, forexample.

[0054] To reproduce data recorded in frames, the present inventiontransfers result information for detection of synchronization code forthe first synchronization code in each frame with the demodulated framedata to the error correcting circuit block, stores this data indifferent memory areas, and applies erasure correction using thesedetection results of synchronization codes during error correction.Error correction is thereby improved, and data can be reproduced withhigh reliability.

[0055] Other objects and attainments together with a fullerunderstanding of the invention will become apparent and appreciated byreferring to the following description and claims taken in conjunctionwith the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0056] The present invention will become readily understood from thefollowing description of preferred embodiments thereof made withreference to the accompanying drawings, in which like parts aredesignated by like reference numeral, and in which:

[0057]FIG. 1 is a schematic drawing showing the structural configurationof a recording medium according to a first embodiment of the invention;

[0058]FIG. 2 is a block diagram showing a playback device according to afirst embodiment of the invention;

[0059]FIG. 3 is a block diagram showing the internal structure of amemory controller 205;

[0060]FIG. 4 is a schematic drawing of the memory map for buffer memory206 in a first embodiment of the invention;

[0061]FIG. 5 is a timing chart showing an example of internal signalchange when a frame is dropped in a first embodiment of the invention;

[0062]FIG. 6 is a timing chart showing an example of internal signalchange when a frame is inserted in a first embodiment of the invention;

[0063]FIG. 7 is a flow chart of buffer memory storing control whenframes slip in a first embodiment of the invention;

[0064]FIG. 8 shows an example of the recording data format of arecording medium according to a first embodiment of the invention;

[0065]FIG. 9 is a schematic diagram of a method for recording discaddress information to a recording medium according to a firstembodiment of the invention;

[0066]FIGS. 10A to 10C are schematic diagrams of the frame datastructure in a second embodiment of the invention;

[0067]FIG. 11 is a schematic diagram of the optical disc format in asecond embodiment of the invention;

[0068]FIG. 12 is a flow chart of the playback method in a secondembodiment of the invention;

[0069]FIGS. 13A and 13B show the data structure in a first example of aplayback method according to the second embodiment of the invention whenthe detection result of synchronization code is normal;

[0070]FIG. 14 shows how the result information for detection ofsynchronization code and the demodulated frame data in FIG. 13 arestored;

[0071]FIGS. 15A and 15B show the data structure in a second example of aplayback method according to the second embodiment of the invention whenthe detection result of synchronization code is not detected;

[0072]FIG. 16 shows how the result information for detection ofsynchronization code and the demodulated frame data in FIG. 15 arestored;

[0073]FIGS. 17A and 17B show the data structure in a third version ofthe first example of a playback method according to the secondembodiment of the invention when the detection result of synchronizationcode is out-of-step synchronization;

[0074]FIG. 18 shows how the result information for detection ofsynchronization code and the demodulated frame data in FIG. 17 arestored;

[0075]FIGS. 19A and 19B show the data structure in a fourth version ofthe second example of a playback method according to the secondembodiment of the invention when the detection result of synchronizationcode is out-of-step synchronization;

[0076]FIG. 20 shows how the result information for detection ofsynchronization code and the demodulated frame data in FIG. 19 arestored;

[0077]FIGS. 21A and 21B show the data structure in a fifth version of athird example of a playback method according to the second embodiment ofthe invention when the detection result of synchronization code isout-of-step synchronization;

[0078]FIG. 22 shows how the result information for detection ofsynchronization code and the demodulated frame data in FIG. 21 arestored;

[0079]FIGS. 23A and 23B show the data structure in a sixth version of afourth example of a playback method according to the second embodimentof the invention when the detection result of synchronization code isout-of-step synchronization;

[0080]FIG. 24 shows how the result information for detection ofsynchronization code and the demodulated frame data in FIG. 23 arestored;

[0081]FIGS. 25A and 25B are schematic diagrams describing generating aerasure point in a playback method according to a second embodiment ofthe invention;

[0082]FIG. 26 is a block diagram showing the configuration of a playbackcircuit in a third embodiment of the invention; and

[0083]FIG. 27 is a block diagram showing the configuration of an opticaldisc playback device according to a fourth embodiment of the invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0084] Preferred embodiments of the present invention are describedbelow with reference to the accompanying figures using an optical discmedium by way of example as the recording medium of the invention.

[0085] Embodiment 1

[0086] A playback method, a playback control circuit and a playbackdrive for a recording medium according to a first embodiment of thepresent invention are described below. FIG. 1 is a schematic diagram ofan optical disc 11 used as the recording medium in this embodiment ofthe invention. As shown in FIG. 1 a guide groove (called a “groove”below) is formed in a spiral on the recording surface of the opticaldisc 11. A data track 12 is formed by this groove.

[0087] Recorded data is recorded to the data track 12 in recordingblocks 13 of plural fixed-length frames. Address information for eachrecording block 13 is prerecorded in each data track 12 using a wobbledgroove or other known change in the groove shape. Though not shown inthe figure, a phase-change recording film is formed on the recordingsurface of the optical disc 11. A local temperature increase caused bythe recording device focusing a laser beam spot on the recording filmproduces a phase change between crystalline and amorphous phases wherebyinformation is recorded.

[0088] The address information includes information identifying thelocation of the recording block 13, which as noted above is the datarecording unit. The device reading the optical disc reads the data track12 to read the address information, and thereby identifies the locationof the recording block 13.

[0089] Recorded data is recorded in recording block 13 units on thepreformed grooves. Each recording block 13 consists of pluralfixed-length frames. A synchronization code 15 is located at thebeginning of each frame 14.

[0090]FIG. 8 shows an example of the recorded data structure in onesector after modulation. One sector contains 26 consecutive frames and atotal 2366 bytes with each frame containing 91 data bytes. This totalbyte count includes 2048 user data bytes, and redundant data such as thedata ID and error correcting code parity bytes. Modulation converts 8binary bits into 16 channel bits, and 91 binary data bytes thereforebecome a modulated code stream of 1456 channel bits. A synchronizationcode of 32 channel bits is prepended to the beginning of the modulatedcode, creating the recording data for one frame. One frame thereforecontains 1488 channel bits.

[0091] As shown in FIG. 8 one of eight synchronization codes is usedaccording to the location of each frame in the sector. Thesynchronization codes include a specific (14T+4T) mark/space patternpreceded by a specific pattern identifying the synchronization codetype. The synchronization code in frame 1, that is, the first frame ineach sector, is called SY0, the synchronization code for frame 2 is SY5,and so forth for frames 3 to 26, assigning a different pattern forsignals SY1 to SY7 according to the frame number and whether the framenumber is even or odd. It is therefore known, for example, that fourframes from the sector start have passed if the synchronization codesfor three consecutive frames are {SY5, SY1, SY5}, and that twelve framesfrom the sector start have passed if the synchronization codes for threeconsecutive frames are {SY5, SY1, SY6}.

[0092] One method of recording address information is shown in FIG. 9.The preformed guide groove is wobbled at a known spatial frequency (a186 channel bit period in this example), and address information isrecorded according to whether a pit is formed or is not formed at aspecific period unit (eight wobble periods, equivalent to one frame, inthis example) in the land between one wobble groove 41 and the adjacentwobble groove 41. The pits recorded to these lands are called landprepits 43. The address information recorded by these land prepits 43 iscalled a “prepit address.” As shown by the data track 12 and recordingblocks 13 in FIG. 1, there is a known correlation between prepitaddresses and recording blocks 13. This known correlation means that thelocation of a recording block 13 is relative to a specified number ofprepit addresses, and there is a 1:1 correlation between each recordingblock 13 and this specified number of prepit addresses. Morespecifically in this example, two prepit addresses are assigned to onerecording block 13, which is the data recording unit, each twoconsecutive prepit addresses form a prepit address pair, and there is a1:1 relationship between a prepit address pair and a particularrecording block 13.

[0093] The relationship between the address information created by thesepreformed land prepits and data recorded to the phase-change film isdescribed briefly next. When data is recorded the recorder records thesynchronization code at the beginning of the data frame eithersubstantially aligned with or at a location having a known physicalrelationship to the beginning of the land prepit information unit. Thisenables the playback device to predict where the data is recorded byreading this address information during data playback.

[0094] A specific method of predicting the data recording position whilereading this address information is described next. There are twoperiods storing a value meaningful as address information, that is,periods where the prepit address changes, in one ECC block (recordingblock). The data recording location therefore cannot be predicted withsector or frame unit accuracy by simply reading this addressinformation.

[0095] A prediction counter is therefore used to accurately predictwhere data is recorded. This prediction counter includes frame lengthcounter FLCNT for measuring the length of one frame, frame counter FRCNTfor counting the number of frames, and sector counter SCNT for countingthe number of sectors. At least the frame length counter FLCNT thatmeasures the length of one frame uses the channel clock extracted fromthe wobble period in order to reduce prediction counter error.

[0096] The frame length counter FLCNT is a loop counter that incrementsfrom 0 to 1931 every 11 bits, and then returns to 0. The frame counterFRCNT is also a loop counter, increments from 0 to 25 every 5 bits, andthen returns to 0. The sector counter SCNT is also a loop counter,increments from 0 to 15 every 4 bits, and then returns to 0. Eachcounter can preset the counter value at the read timing of the landprepit address information. This anticipates processing delay by theread circuit, and enables adjusting the count to a value equivalent tothe predicted location of the recorded data when the land prepit addressinformation is read. The “predicted location of the recorded data” asused herein denotes the position relative to the start of one ECC blockin the form {sector number-frame number-channel bit number}.

[0097] After the prediction counter is thus preset in conjunction withreading the address information, the loop counters can be used topredict where the data is recorded. Furthermore, the data location canbe accurately predicted insofar as the light beam remains on track andphase synchronization between the wobble and the channel clock extractedfrom the wobble is not completely lost.

[0098] Advantages of predicting the data recording location from addressinformation recorded with a preformed groove pattern are described next.The period of the wobble groove or address information carrier isgenerally at least approximately ten times the average T (averagemark/space length) of the modulated code stream, and at least two timesthe maximum T (maximum mark/space length). This is to avoid frequencyinterference between the recorded data and wobble pattern, and resultingdegradation of playback signal quality. Because the wobble frequency isbelow the frequency band of the recorded data, less wobble data is lostthan recorded data when the recording surface of the disc is scratched,for example. A PLL based on phase comparison at the wobble edge istherefore more resistant to disc defects, scratches, and dust than a PLLbased on phase comparison at the recorded data edge. In other words, aclock signal derived from the wobble signal is notably more stable thana clock signal derived from the recorded data.

[0099]FIG. 2 is a block diagram showing the configuration of a playbackdevice according to a first embodiment of the invention. Operation ofthis playback device is described next.

[0100] The signal reading means 21 first emits a light beam to theoptical disc 11, and reads a signal from the beam reflection. The signalreading means 21 extracts signal RF1 reproducing a signal in thetracking direction using a known push-pull method in order to read thewobble and land prepit signal described above, and signal RF2reproducing the change in reflectivity as a signal in order to read therecorded data.

[0101] Signal RF1 is sent to the address information playback means 22,which extracts the wobble signal component and acquires the channelclock using a phase-locked loop (PLL) or other technique. The addressinformation playback means 22 also extracts the land prepit signalcomponent from signal RF1, and reproduces and decodes the addressinformation from the land prepit signal. The prediction counter notshown begins operating and outputs a counter value representing thepredicted location of the recorded data after a phase-locked channelclock is derived from an internal wobble signal PLL (not shown in thefigure) and the address information is correctly decoded from the landprepit signal. The value of the output counter preferably alwayscontains the sector count SP, frame count FP, and channel count CP.

[0102] Signal RF2 is sent to the synchronization means 23, whichextracts the signal component of the recorded data and derives thechannel clock and channel data using a phase-locked loop (PLL) or othertechnique. The synchronization means 23 also detects the specificpattern (14T+4T in this example) of the synchronization code from thechannel data, and outputs synchronization code SY. To improve thereliability of detecting this specific pattern, this synchronizationcode SY is preferably output after detecting plural consecutive framesas needed. The synchronization means 23 also preferably has internalmeans for measuring the synchronization code detection interval, andmeans for generating a synchronization code detection prediction window.This makes it possible to prevent outputting a pseudo synchronizationcode SY at the wrong detection interval, and to internally interpolatethe synchronization code SY from the previously detected signal when asynchronization code is not detected when expected.

[0103] One method of interpolating and outputting the synchronizationcode SY when the synchronization code is not actually detected is basedon the synchronization clock of the playback PLL. This method relies ona counter for counting the channel clock (1488 channel bits in thisexample) equivalent to the length of one frame from the point at whichthe previous synchronization code was detected, and interpolates thesynchronization code SY using the output of this counter. This countercan also be used as the above-noted means for measuring thesynchronization code detection interval or the means for generating theprediction window.

[0104] In addition to detecting a specific pattern from thesynchronization code, the synchronization means 23 also detects thesynchronization code type and outputs synchronization code type signalSYID. With the recorded data format shown in FIG. 8, for example, thereare eight synchronization code types SY0 to SY7. The synchronizationmeans 23 therefore also outputs synchronization code type signal SYID=0to 7 according to the detected signal type SY0 to SY7, and outputsSYID=8 if a playback error in the synchronization code preventsidentifying the signal type.

[0105] The synchronization means 23 also outputs synchronization statesignal LOCK according to the frame synchronization detection state. Inthis example synchronization state signal LOCK=1 when framesynchronization is normal, and LOCK=0 when there is a problem with framesynchronization, such as when frame synchronization is out of step. Morespecifically, LOCK=0 when the synchronization code is not detected for aspecified number of consecutive frames.

[0106] The synchronization code SY is output to demodulator 24, whichuses it as the timing signal for starting to demodulate the channel datato binary data. The demodulator 24 then sends the demodulated data DEMDTand data strobe signal DTEN to memory controller 25. The data strobesignal DTEN is used for the demodulated data DEMDT update timing.

[0107] The memory controller 25 works to correctly store the demodulateddata DEMDT to buffer memory 26. The memory controller 25 receives thesynchronization code SY, synchronization code type signal SYID, andsynchronization state signal LOCK from synchronization means 23, and thepredicted recorded data location (sector count SP and frame count FP)from address information playback means 22, and uses these signals tocontrol where the demodulated data DEMDT is stored.

[0108] The buffer memory 26 specifies where the data is stored (the bytelocation for reading or writing) using memory address MADR, and thememory controller 25 controls where demodulated data DEMDT is stored bycontrolling buffer memory 26 address MADR.

[0109]FIG. 3 is a block diagram showing the internal configuration ofthe memory controller 25. The frame number detection means 31 detectsthe number of the frame from the beginning of the sector based on thesynchronization code SY and synchronization code type signal SYID fromsynchronization means 23. More specifically, it gets the synchronizationcode type signal SYID at the synchronization code SY timing, and outputsthe frame number FRNUM identified from multiple previous frames based onthe synchronization code type SYID. Referring to the recorded dataformat shown in FIG. 8, for example, FRNUM is a value from 0 to 25corresponding to the number of frames from the beginning of the sectorsuch that FRNUM=3 if the synchronization code type signals SYID for thethree previous frames were {SY5, SY1, SY5}, and FRNUM=11 if the signalswere {SY5, SY1, SY6}. If the synchronization code type signal SYID=8(i.e., unknown type) or the combination of SYID values does not identifyany particular frame, then FRNUM=26 denoting an unknown frame number.

[0110] The byte counter 32 counts the number of bytes in each frame. Thebyte counter 32 clears byte count BC (=0) at the synchronization code SYfrom synchronization means 23, and increments the byte count BC one eachtime the demodulator 24 outputs data strobe signal DTEN=1. The bytecounter 32 continues counting until BC=91, at which time it clears bytecount BC to 0 at the next synchronization code SY.

[0111] The frame counter 33 counts the number of frames in one sector.When the beginning of a sector is detected, such as when frame numberdetection means 31 outputs frame number FRNUM=0, frame counter 33 clearsframe count FC to 0, increments frame count FC one at thesynchronization code SY from synchronization means 23, and resets framecount FC to 0 at the next synchronization code SY when FC=25. The frameslip detector 35 can also control correcting frame count FC to aspecific value. The frame count FC counts a clock based on thepreviously detected synchronization code SY, and increments when thenext synchronization code SY is detected. If the next synchronizationcode SY is not detected, counting continues and the frame count FC isincremented using the original clock.

[0112] The sector counter 34 counts the number of sectors in one ECCblock. The sector counter 34 clears the sector count SC to 0 at thestart of an ECC block, increments sector count SC one simultaneously toframe counter 33 resetting frame count FC from 25 to 0, and clears thesector count SC to 0 at the next synchronization code SY when SC=15 andFC=25. The sector count SC can also be corrected to a specified valuebased on output from the frame slip detector 35. The sector count SCcounts a clock based on the previously detected synchronization code SY,and increments when a specific number of synchronization codes SY hasbeen detected. If the synchronization code SY is not detected, countingcontinues according to the original clock and sector count SC incrementsat a predetermined time.

[0113] The frame slip detector 35 monitors change in the synchronizationstate signal LOCK, detects recovery from out-of-step synchronization,and looks for frame slip by comparing predicted recorded data locationvalues SP and FP, sector count SC, and frame count FC.

[0114] It should be noted that the synchronization code SY isinterpolated and output based on the channel clock synchronized to theplayback PLL when the synchronization code is not detected, and the bytecounter 32, frame counter 33, and sector counter 34 therefore operate asdescribed above whether the synchronization code is detected or notdetected.

[0115] The address convertor 36 converts the byte count BC, frame countFC, and sector count SC to a memory address MADR specifying a memoryaddress in buffer memory 26.

[0116] FIFO 37 is a first-in first-out memory device for holding aspecified time and then outputting the demodulated data DEMDT. FIFO 37delays output of demodulated data DEMDT this specified time due to thedelay required for the address convertor 36 to process and output memoryaddress MADR, and then outputs demodulated data DEMDT as storing dataDATA. The memory address MADR and storing data DATA are therefore outputat the same time to buffer memory 26 and the demodulated data can bestored to the correct memory address.

[0117]FIG. 4 shows an example of a memory map for buffer memory 26according to the present embodiment. The number of bytes that can storeuser data in one frame is indicated in the horizontal direction anddenoted as m bytes. The number of frames in one ECC block is denoted bythe number of rows in the vertical direction, and is shown as n frames.To achieve the recording data format shown in FIG. 8, m=91 and n=416.The data from one ECC block can be stored by frame unit in thedemodulation order by managing buffer memory 26 using a memory map suchas shown in FIG. 4.

[0118] When storing the demodulated data from a target ECC block tobuffer memory 26, the target ECC block is found by decoding the data IDin the recorded data, and the data is then stored sequentially from thebeginning to buffer memory 26. The beginning of an ECC block is found bydetecting the synchronization code type and decoding the data ID, andthe first memory address for the demodulated data in each frame iscontrolled with synchronization code SY.

[0119] What happens when playback signal quality for the recorded datatemporarily deteriorates and synchronization code detection and data IDdecoding are not possible for several frames or an entire sector isconsidered next. In this case the internal playback PLL of thesynchronization means 23 may be out-of-step. Whether the PLL isout-of-step cannot be easily determined when consecutive synchronizationcodes cannot be detected because the recorded data contains signals ofvarious mark and space lengths in the modulated code stream.

[0120] On the other hand, because the period of the wobble signalderived from signal RF1 is sufficiently longer than the period of therecorded signal derived from signal RF2, the internal wobble signal PLLof the address information playback means 22 is more stable than theplayback PLL when the signal is degraded by, for example, scratches ordust on the disc. Synchronization is therefore unlikely to becomeout-of-step in these cases. Furthermore, even if synchronization isout-of-step, if the wobble signal is derived as a signal with a specificfrequency near the period of the carrier, a phase comparison of thewobble signal and PLL clock can easily determine if the wobble signalPLL is out-of-step.

[0121] The playback device can therefore determine which frame (framenumber) in the current ECC block is to be demodulated from the locationof the recorded data predicted by the address information playback means22 insofar as the wobble signal PLL, which is more stable than theplayback signal PLL, is in phase even if synchronization code detectionis not possible because of degraded signal quality.

[0122] For example, if demodulated data in a particular ECC block is tobe stored to buffer memory 26, the address information playback means 22can determine the memory address nx (where 0<=nx<=415) in the buffermemory that will store the data as

nx=SPx*FPx

[0123] where predicted sector position SPx is an integer in the range0<=SPx<=15, and predicted frame position FPx is an integer in the range0<=FPx<=25.

[0124] The location of recorded data in an ECC block can therefore bepredicted in real time using the reproduced address information andsynchronization clock from the wobble signal PLL.

[0125] Furthermore, the memory address of the demodulated data in thebuffer memory can be controlled at the frame unit level by using thepredicted position of the recorded data. Demodulated data can thereforebe appropriately stored to the buffer memory even if consecutivesynchronization codes cannot be detected from the recorded data.

[0126] When a frame is dropped due to degraded signal quality in therecorded data, storing controlling data to the buffer memory isdescribed next.

[0127] In the first example considered below the playback signal PLLgoes out-of-step in the low frequency direction, the synchronizationcode continues undetected for the time equivalent of seven frames, andthere is a frame slip (loss) of one frame.

[0128]FIG. 5 is a timing chart illustrating the loss of one frame due toframe slip. When the playback PLL goes out-of-step, pattern detectiondoes not occur when the synchronization code should normally be detectedas shown in the figure. The synchronization code is thereforeinterpolated based on the PLL synchronization clock, and theinterpolated synchronization code SY is output in the time-delaydirection. The synchronization code type signal SYID is therefore set to8 (unknown type) and the frame number FRNUM is set to buffer memory 26(unknown frame number).

[0129] In the example shown in FIG. 8, when synchronization state signalLOCK =1 (normal synchronization) and the synchronization code is thenundetected for four consecutive frames or more, synchronization is knownto be out-of-step and LOCK therefore goes to 0 (out-of-stepsynchronization). If when synchronization state signal LOCK=0 thesynchronization code is then detected from two consecutive frames, LOCKagain goes to 1, denoting normal synchronization.

[0130] Furthermore, when synchronization state signal LOCK changes from0 to 1 (i.e., when synchronization is recovered), recording positionprediction signals SP and FP, sector count SC, and frame count FC arecompared, and if (SP=SC and FP=FC), it is assumed that only a frame sliphas occurred, and the memory address in the frame data buffer memory 206is shifted one frame unit.

[0131] More specifically in this example, when LOCK goes from 0 to 1,SP=2, FP=5, SC=2, and FC=4, the value of frame count FC is one less thanthe recording position prediction signal FP, and it is known that oneframe was dropped while synchronization was out of step. The frame countFC is therefore corrected from the current value of 4 to 5. As a result,the memory address MADR output by address convertor 36 can beautomatically changed to point to the correct memory address. It istherefore possible to immediately store data to the correct memoryaddress when synchronization is restored.

[0132] It should be noted that while the recording position predictionsignals and counter values indicating the buffer memory address arecompared at the frame unit level in this embodiment, comparison at thebyte unit level is also possible. However, because the correlationbetween these can vary somewhat due to variation in the recordingposition by the recording device and PLL jitter in the playback device,it is preferable to use as the unit of comparison a unit thatpotentially produces less error considering the potential for thisvariation.

[0133] In the next example below the playback signal PLL goesout-of-step in the high frequency direction, the synchronization codecontinues undetected for the time equivalent of ten frames, and there isa frame slip (misinsertion) of two frames.

[0134]FIG. 6 is a timing chart showing insertion of two frames. As shownin the figure, the playback PLL goes out of sync, pattern detection doesnot occur when the synchronization code should normally be detected, thesynchronization code is interpolated based on the PLL synchronizationclock, and the interpolated synchronization code SY is output in thetime-advanced direction.

[0135] The state change in the synchronization state signal LOCK is thesame as shown in FIG. 5 in this example. When the synchronization statesignal LOCK goes from 0 to 1, i.e., when synchronization is restoredfrom an out-of-step state, the recording position prediction signals areSP=3 and FP=7, sector count SC=3 and frame count FC=9, data iserroneously inserted while synchronization is out-of-step, and it isknown that two extra frames have been stored to the buffer memory. Theframe count FC is therefore corrected from the current value of FC=9 toFC=7. The memory address MADR output from address convertor 36 cantherefore be automatically changed to point to the correct memoryaddress. It is therefore possible to immediately store data to thecorrect memory address when synchronization is restored.

[0136]FIG. 7 is a flow chart of the process shown in the timing chartsin FIG. 5 and FIG. 6 from the perspective of buffer memory storingcontrol by the memory controller 25. The flow chart shown in FIG. 7 isdescribed next below.

[0137] (a) Data playback of the target ECC block starts, andsynchronization state signal LOCK denoting an out-of-step state is setto normal synchronization (LOCK=1).

[0138] (b) The data and block address information is acquired (S01).

[0139] (c) Whether the synchronization code SY was detected or not isthen determined (S02). If the synchronization code SY was not detected,control loops back to step S01 to acquire data for the next frame. Ifthe synchronization code SY is not detected, LOCK=0 becausesynchronization is determined to be out-of-step, and synchronizationcode SY is interpolated and output based on the synchronization codedetected immediately before. If the synchronization code SY wasdetected, LOCK=1 because synchronization is normal.

[0140] (d) The sector count SP predicting the recording position of eachsector in the block from the address information, and the frame count FPpredicting the recording position of each frame in the sector, are thenupdated. The sector count SC and frame count FC are then updated basedon the detected or interpolated synchronization code SY (S03).

[0141] (e) Recovery of frame synchronization, or more specifically achange in the synchronization state signal LOCK from 0 to 1, is thendetected (S04). If there is a change from an out-of-step state (LOCK=0)to a normal synchronization state (LOCK=1), synchronization is restoredand S04 returns yes. If LOCK=1 remains true because normalsynchronization continues (i.e., synchronization was not lost), S04returns no.

[0142] (f) The recording position prediction signals SP and FP, sectorcount SC, and frame count FC are then compared (S05). If the valuesmatch, frame slip has not occurred, and S05 returns yes.

[0143] (g) However, if there is a mismatch between any of these values,a frame slip has occurred. The value of the sector position predictionsignal SP is therefore substituted for sector count SC, and the value ofthe frame position prediction signal FP is substituted for frame countFC (S06).

[0144] (h) Data is then recorded to the memory address corresponding tothese SC and FC values.

[0145] (i) Whether operation is completed is then determined (S08). Ifoperation continues, the process loops back to the data and addressinformation acquisition step (S01). If operation ends, the terminationprocess executes.

[0146] The process described with reference to the flow chart in FIG. 7can quickly correct the buffer memory address as soon as synchronizationrecovers from a frame slip whenever a frame slip occurs.

[0147] More specifically, when compared with methods that use onlyinformation reproduced from the recorded data, the recording address canbe corrected more quickly and reliably by predicting the recordingaddress using data separate from the data signal reproduced from therecorded data, i.e., information acquired from the wobble groove andland prepits, and detecting and correcting for frame slip.

[0148] Furthermore, data loss caused by frame slip can be minimizedwithout complicating buffer memory management because the buffer memoryunit can be corrected at the data frame level.

[0149] It will thus be apparent from the preceding description that amethod and apparatus according to this embodiment of the invention canconsistently predict the location of recorded data from a preformedwobble groove and land prepits.

[0150] Furthermore, when frame slip results from the playback PLL goingout-of-step and synchronization is then restored, the method andapparatus of this embodiment can also determine whether frame slip hasoccurred by comparing the predicted location of the recorded data withthe address where the demodulated data is stored to buffer memory.

[0151] Yet further, when the buffer memory address shifts due to frameslip, the method and apparatus of this embodiment can also use thepredicted location of the recorded data to assure that subsequentdemodulated data is stored to the correct address.

[0152] In the above-described embodiment of the invention frame slipdetection and buffer memory address correction are accomplished usingrecording address prediction signals. The invention shall not be solimited, however, and a method that also looks at the data ID of therecorded data and the synchronization code type (and whether the typematches) could additionally be used. Additionally using a method thatlooks at the data ID of the recorded data and the synchronization codetype (and whether the type matches) is particularly effective when, forexample, the wobble signal PLL is out-of-step before or after frame slipoccurs, and when it is difficult to predict the address of the recordeddata due to the poor quality of the land prepits.

[0153] An optical disc is also used by way of example as the recordingmedium in the present embodiment of the invention, but the inventionshall not be so limited. More specifically, the object of the inventioncan be achieved using any recording medium that, similarly to the wobblegroove and land prepits of the above-described embodiment, has both achannel for recording user data and another separate channel on the samerecording medium such that a reading device can read both channelssubstantially simultaneously, and can predict where data is stored inthe user data recording channel based on information read from the otherchannel because there is a known correlation between the informationacquired from the other separate channel and where user data is recordedon the user data recording channel.

[0154] Yet further, this other separate channel is preferably morerobust, meaning it is more resistant to errors resulting from scratches,dust, or defects in the recording medium, than the user data recordingchannel.

[0155] The buffer memory map described above is also simply based onframe units, but the invention shall not be so limited. In practice,data will be stored appropriately to the encoding/decoding processes ofthe disc drive as determined by the error correcting code (product code,interleaved, or other). For example, the correction process can be mademore efficient by dividing memory space into parts equivalent to thedata bytes and parity bytes in the error correcting code. The processcan also be accelerated by deinterleaving the demodulated data whilestoring it to buffer memory. In any case, this can be handled bymodifying the internal configuration of the means for converting thememory address applied to the buffer memory, and differences relating tothe specifics of the buffer memory map have no direct effect on thesubstance of the present invention.

[0156] Embodiment 2

[0157] A playback method according to a second embodiment of theinvention is described next. FIG. 10A to FIG. 10C show the frame dataformat in this second embodiment. FIG. 10A shows the format of thesector error correcting code, each error correcting code 101 adding 16bytes of parity data 103 to each 128 bytes of user data 102. One sectorcontains eight error correcting code 101 blocks. The error correctingcode 101 is coded in the column direction and recorded in the rowdirection, thus interleaving the code so as to improve the ability tocorrect burst errors.

[0158] The error correcting code 101 is coded using a known Reed-Solomoncoding method. The 16-byte parity data 103 has an error correctingcapacity of up to 8 bytes. By erasure correction, error correcting of upto 16 bytes is possible. Eight error correcting code 101 blocks producea 1 KB sector, and the sector is the smallest unit used for reading andwriting.

[0159]FIG. 10B shows the frame data format dividing the above errorcorrecting code into rows. The eight error correcting code 101 blocks inone sector are thus interleaved and split into frame data 104 of 8 bytesper frame.

[0160]FIG. 10C shows the frame structure in which frame data 104 isstored as modulated frame data 105. A synchronization code 106 isprepended to each modulated frame data 105 block. The modulation methodused here is the same (8,16) modulation used with DVD media, i.e., 8bits are converted to 16 bits and an 8-byte frame data 104 block isconverted to (8*16=) 128 bits of modulated frame data 105. Thesynchronization code 106 is 32 bits long and comprises a known specificpattern that never appears in (8,16) modulated code, and a frame number.One frame thus comprises (32+128=) 160 bits, and one sector comprises atotal 144 frames.

[0161] It will be obvious that the synchronization code shall not belimited to this configuration. Multiple specific patterns could be usedto write a different synchronization code in each frame, and thesequence of these specific patterns could be detected from thesynchronization codes in multiple frames to determine the number of eachframe.

[0162] This frame structure is commonly used in optical disc media sothat synchronization can be corrected when bit slip occurs due to a discdefect or scratch, for example, by detecting the first synchronizationcode in each frame and resynchronizing.

[0163]FIG. 11 shows the format of an optical disc and how a sector shownin FIG. 10 is recorded to the optical disc 201. As shown in FIG. 11,each sector 202, which is the smallest recording/playback unit, isrecorded to the optical disc 201 divided into 144 frames, each framecomprising a 32-bit synchronization code 204 and 128-bit modulated framedata 203.

[0164]FIG. 12 is a flow chart of the playback method of this secondembodiment of the invention used to read an optical disc recorded asshown in FIG. 10 and FIG. 11. This playback method is described nextwith reference to FIG. 12.

[0165] (a) The synchronization code is first detected from the playbacksignal read from the disc for frame synchronization (framesynchronization step 301). Because the synchronization code is recordedusing a specific pattern, the synchronization code can be detected bydetecting a match with the playback signal.

[0166] Frame synchronization as used here means that the number of eachframe and the beginning of each frame, and the beginning of eachmodulated frame data block, are identified from the playback signal.

[0167] (b) Result information for detection of synchronization code 311denoting the detection result of synchronization code is created foreach modulated frame data block (result information for detection ofsynchronization code generating step 302). There are three detectionresult of synchronization codes, normal detection, out-of-stepdetection, not detected, which are encoded in the result information fordetection of synchronization code 311 as the two-bit values 00, 10, and01, respectively.

[0168] i) Normal Detection

[0169] The number of bits from the synchronization code in thepreviously detected frame is also counted during synchronization codedetection. Because one frame is 160 bits long, the synchronization codefor the next frame should be detected precisely 160 bits after theprevious synchronization code. If it is so detected, detection result ofsynchronization code 309 is set to normal because synchronization is notout-of-step from one frame to the next.

[0170] ii) Out-of-Step Detection

[0171] If the synchronization code is detected at a time other than 160bits after the beginning of the previous frame, frame synchronization iscorrected to resynchronize based on the newly detected synchronizationcode. As a result of this frame synchronization, the demodulationprocess described below is applied to the 128-bit modulated frame data308 based on the identified frame start position. The detection resultof synchronization code 309 is set to out-of-step detection. Note thatout-of-step synchronization could be either advanced or delayedsynchronization.

[0172] iii) Undetected

[0173] If the synchronization code is not detected, the currentsynchronization phase is held and detection result of synchronizationcode 309 is set to undetected.

[0174] As further described below the result information for detectionof synchronization code 311 is 8 bits (one byte), and the remaining sixbits are used to substantially identify the frame number. The bit lengthand coding method of the result information for detection ofsynchronization code 311 shall not be limited to the above. The bitlength could, for example, be increased so that the frame number can becompletely identified.

[0175] (c) The 128-bit modulated frame data 308 is then demodulatedbased on the frame start position identified as a result of framesynchronization. This demodulation step 303 demodulates the modulatedframe data, and thus outputs demodulated frame data 310.

[0176] (d) The result information for detection of synchronization code311 is prepended to the beginning of each demodulated frame data blockand sent to the error correcting circuit block (adding step 304 foradding the detection result of synchronization code).

[0177] (e) The transferred demodulated frame data and result informationfor detection of synchronization code 311 are stored in separate areasin DRAM or other memory device (memory step 305).

[0178] (f) To execute erasure correction, a erasure pointer identifyingthe error location is generated from the result information fordetection of synchronization code 311 stored to memory (erasure pointergenerating step 306). The erasure pointer is generated using only theresult information for detection of synchronization code 311 in thisexample, but a means for predicting the locations of other errors couldalso be used.

[0179] (g) The erasure pointer is then used for erasure correction inthe error correction step 307. Error correction capacity is increased atmost twice by applying erasure correction.

[0180] The demodulated frame data stored to memory can then be read frommemory and the correct data can be reproduced because error correctinghas already been applied.

[0181] The steps from the frame synchronization step 301 to the memorystep 305 are described in detail next below with reference to FIG. 13 toFIG. 24.

EXAMPLE 1

[0182]FIG. 13 and FIG. 14 show a first example in which the detectionresult of synchronization code is normal detection. FIG. 13A shows thedata format of the playback signal input in frame synchronization step301, and FIG. 13B shows the data format of the demodulated frame dataand result information for detection of synchronization code passed fromadding step 304 for adding the detection result of synchronization codeto memory step 305.

[0183] In FIG. 13 the synchronization code 402 for frame m+1 is detectedat precisely 128+32 bits from when the synchronization code 401 forframe m was detected. More specifically, the synchronization time offrame m+1 predicted by counting the clock from when the synchronizationcode 401 for frame m was detected matches the timing at whichsynchronization code 402 was actually detected.

[0184] In this case the detection result of synchronization code fromframe synchronization step 301 is normal (00), and the resultinformation for detection of synchronization code generating step 302sets the low two bits of the result information for detection ofsynchronization code 406 for frame m+1 to 00. Because the resultinformation for detection of synchronization code is 1 byte (8 bits)long, the highest 6 bits of the signal store the lowest six bits of theframe number (though not shown in the figure). In this example,therefore, result information for detection of synchronization code 406stores the lowest six bits of m+1.

[0185] Based on frame synchronization by frame synchronization step 301,the modulated frame data 404 is demodulated by the demodulation step303, resulting in demodulated frame data 408. Because (8,16) modulationis used in this second embodiment of the invention, the 128-bitmodulated frame data is converted to 8 bytes of demodulated frame data.

[0186] The adding step 304 then prepends the result information fordetection of synchronization code to each demodulated frame data blockand sends the result to the memory step 305 for writing to memory in theerror correcting circuit block. Because the result information fordetection of synchronization code is added to each demodulated framedata block, correlation to the detection result of synchronization codefor the demodulated frame data is also simple.

[0187]FIG. 14 shows storing the transferred demodulated frame datahaving the result information for detection of synchronization codeprepended to the beginning thereof as shown in FIG. 13. As shown in FIG.14 the result information for detection of synchronization code and thedemodulated frame data are stored to separate areas in memory.

[0188] It will be obvious that storing data to different areas can beaccomplished by storing the data to different blocks in the same memorydevice, or by storing the data to different memory devices.

[0189] The result information for detection of synchronization code anddemodulated frame data are stored by frame number to a specific addressin each memory area. For example, the lowest two bits of resultinformation for detection of synchronization code 502 for frame m+1 are00, and the data is stored to the address specified for frame m+1. Thedemodulated frame data 503 for frame m+1 is likewise stored to theaddress specified for frame m+1. Note that the demodulated frame dataand corresponding result information for detection of synchronizationcode are stored linked to each other.

EXAMPLE 2

[0190]FIG. 15 and FIG. 16 show a second example in which the detectionresult of synchronization code is “undetected”. FIG. 15A shows the dataformat of the playback signal input in frame synchronization step 301,and FIG. 15B shows the data format of the demodulated frame data andresult information for detection of synchronization code passed fromadding step 304 for adding the detection result of synchronization codeto memory step 305.

[0191] In the example shown in FIG. 15 synchronization code 602 forframe m+1 is not detected due to a scratch on the disc, for example. Thedetection result of synchronization code returned by framesynchronization step 301 is therefore “undetected” and the low two bitsof the result information for detection of synchronization code 606 forframe m+1 are set to 01 by the result information for detection ofsynchronization code generating step 302. Because the result informationfor detection of synchronization code is 1 byte (8 bits) long, thehighest 6 bits of the signal store the lowest six bits of the framenumber (though not shown in the figure). In this example, therefore,result information for detection of synchronization code 606 stores thelowest six bits of m+1.

[0192] Because the synchronization code 602 was not detected in framesynchronization step 301, the timing predicted by the clock count fromthe detection timing of synchronization code 601 in frame m is used forsynchronization timing. Reliability is accordingly lower in this case.

[0193] Based on frame synchronization by frame synchronization step 301,the modulated frame data 604 is demodulated by the demodulation step303, resulting in demodulated frame data 608. Because (8,16) modulationis used in this embodiment of the invention, the 128-bit modulated framedata is converted to 8 bytes of demodulated frame data.

[0194] The adding step 304 then prepends the result information fordetection of synchronization code to each demodulated frame data blockand sends the result to the memory step 305 for writing to memory in theerror correcting circuit block. Because the result information fordetection of synchronization code is added to each demodulated framedata block, correlation to the detection result of synchronization codefor the demodulated frame data is also simple.

[0195] Demodulated frame data for which the result information fordetection of synchronization code is set to “undetected” can thereforebe easily identified.

[0196]FIG. 16 shows storing the transferred demodulated frame datahaving the result information for detection of synchronization codeprepended to the beginning thereof as shown in FIG. 15. As shown in FIG.16 the result information for detection of synchronization code and thedemodulated frame data are stored to separate areas in memory.

[0197] The result information for detection of synchronization code anddemodulated frame data are stored by frame number to a specific addressin each memory area. For example, the lowest two bits of resultinformation for detection of synchronization code 702 for frame m+1 are01, and the data is stored to the address specified for frame m+1. Thedemodulated frame data 703 for frame m+1 is likewise stored to theaddress specified for frame m+1. Note that the demodulated frame dataand corresponding result information for detection of synchronizationcode are stored linked to each other.

EXAMPLE 3

[0198]FIG. 17 and FIG. 18 show a third example in which the detectionresult of synchronization code is “out-of-step” because a newsynchronization code was detected at a time different from thatpredicted from the timing of the detection result of the immediatelypreceding synchronization code. Synchronization correction is needed inthis case.

[0199]FIG. 17A shows the data format of the playback signal input inframe synchronization step 301, and FIG. 17B shows the data format ofthe demodulated frame data and result information for detection ofsynchronization code passed from adding step 304 for adding thedetection result of synchronization code to memory step 305.

[0200] In the example shown in FIG. 17 the synchronization code 802 forframe m+1 should be detected at 32+128 bits from the timing at whichframe m synchronization code 801 was detected. A drop in the clockfrequency due, for example, to an out-of-step PLL results in thesynchronization code being detected at 32+112 bits, that is, asynchronization delay from the normal timing.

[0201] The detection result of synchronization code is set to “correctsynchronization” by the frame synchronization step 301 in this case, andthe lowest two bits of the result information for detection ofsynchronization code 806 for frame m+1 are set by the result informationfor detection of synchronization code generating step 302 to 10.

[0202] Because the synchronization code 802 was detected at a timingoffset from the timing predicted from the clock, the framesynchronization step 301 corrects synchronization to the timing of thedetected synchronization code 802.

[0203] Based on frame synchronization by frame synchronization step 301,the modulated frame data 804 is demodulated by the demodulation step303, resulting in demodulated frame data 808. Because (8,16) modulationis used in this embodiment of the invention, the 128-bit modulated framedata is converted to 8 bytes of demodulated frame data. The demodulatedframe data 807 for frame m, however, is short bits and is therefore only7 bytes.

[0204] The adding step 304 then prepends the result information fordetection of synchronization code to each demodulated frame data blockand sends the result to the memory step 305 for writing to memory in theerror correcting circuit block. Because the result information fordetection of synchronization code is added to each demodulated framedata block, correlation to the detection result of synchronization codefor the demodulated frame data is also simple.

[0205] Demodulated frame data for which the result information fordetection of synchronization code is set to “correct synchronization”can therefore be easily identified.

[0206]FIG. 18 shows storing the transferred demodulated frame datahaving the result information for detection of synchronization codeprepended to the beginning thereof as shown in FIG. 17. As shown in FIG.18 the result information for detection of synchronization code and thedemodulated frame data are stored to separate areas in memory. Note thatthe demodulated frame data and corresponding result information fordetection of synchronization code are stored linked to each other.

[0207] The result information for detection of synchronization code anddemodulated frame data are stored by frame number to a specific addressin each memory area. For example, the lowest two bits of resultinformation for detection of synchronization code 902 for frame m+1 are10, and the data is stored to the address specified for frame m+1. Thedemodulated frame data 903 for frame m+1 is likewise stored to theaddress specified for frame m+1. Note that the demodulated frame dataand corresponding result information for detection of synchronizationcode are stored linked to each other.

[0208] Because the demodulated frame data for frame m in this case holdsonly 7 bytes, one byte is skipped before storing demodulated frame data904 for frame m+1. It will be obvious that a byte can be thus skipped byproviding a control signal that is sent with the transfer data fromadding step 304 to memory step 305 and indicates whether the transferdata is result information for detection of synchronization code ordemodulated frame data.

[0209] This first example of out-of-step synchronization detectionrefers to a synchronization delay of 1 byte, but also applies tocorrecting any synchronization delay of less than one frame.

EXAMPLE 4

[0210]FIG. 19 and FIG. 20 show a second example of the detection resultof synchronization code being “out-of-step” because a newsynchronization code was detected at a time different from thatpredicted from the timing of the detection result of the immediatelypreceding synchronization code. This example differs from the firstexample of out-of-step synchronization in that a synchronization advanceof less than one frame is corrected.

[0211]FIG. 19A shows the data format of the playback signal input inframe synchronization step 301, and FIG. 19B shows the data format ofthe demodulated frame data and result information for detection ofsynchronization code passed from adding step 304 to memory step 305.

[0212] In the example shown in FIG. 19 the synchronization code 802 forframe m+1 should be detected at 32+128 bits from the timing at whichframe m synchronization code 1001 was detected. An increase in the clockfrequency due, for example, to an out-of-step PLL results in thesynchronization code being detected at 32+144 bits, that is, asynchronization advance from the normal timing.

[0213] The detection result of synchronization code is set to“out-of-step” (10) by the frame synchronization step 301 in this case,and the lowest two bits of the result information for detection ofsynchronization code 1006 for frame m+1 are set by the resultinformation for detection of synchronization code generating step 302 to10.

[0214] Because the synchronization code 1002 was detected at a timingoffset from the timing predicted from the clock, the framesynchronization step 301 corrects synchronization to the timing of thedetected synchronization code 1002.

[0215] Based on frame synchronization by frame synchronization step 301,the modulated frame data 1004 is demodulated by the demodulation step303, resulting in demodulated frame data 1008. The demodulated framedata 1007 for frame m has extra bits in this case, but because theoriginal demodulated frame data has a maximum 8 bytes, only the first 8bytes of the demodulated frame data are transferred.

[0216] The adding step 304 then prepends the result information fordetection of synchronization code to each demodulated frame data blockand sends the result to the memory step 305 for writing to memory in theerror correcting circuit block. Because the result information fordetection of synchronization code is added to each demodulated framedata block, correlation to the detection result of synchronization codefor the demodulated frame data is also simple.

[0217] Demodulated frame data for which the result information fordetection of synchronization code is set to “correct synchronization”can therefore be easily identified.

[0218]FIG. 20 shows storing the transferred demodulated frame datahaving the result information for detection of synchronization codeprepended to the beginning thereof as shown in FIG. 19. As shown in FIG.20 the result information for detection of synchronization code and thedemodulated frame data are stored to separate areas in memory. Note thatthe demodulated frame data and corresponding result information fordetection of synchronization code are stored linked to each other.

[0219] The result information for detection of synchronization code anddemodulated frame data are stored by frame number to a specific addressin each memory area. For example, the lowest two bits of resultinformation for detection of synchronization code 1102 for frame m+1 are10, and the data is stored to the address specified for frame m+1. Thedemodulated frame data 1103 for frame m+1 is likewise stored to theaddress specified for frame m+1.

EXAMPLE 5

[0220]FIG. 21 and FIG. 22 show a third example of the detection resultof synchronization code indicating that synchronization correction isneeded because the next synchronization code was detected at a timedifferent from that predicted from the timing of the immediatelypreceding synchronization code. This fifth example differs from thefirst and second synchronization correction examples above in that asynchronization delay of one whole frame or more is corrected.

[0221]FIG. 21A shows the data format of the playback signal input inframe synchronization step 301, and FIG. 21B shows the data format ofthe demodulated frame data and result information for detection ofsynchronization code passed from adding step 304 to memory step 305.

[0222] In the example shown in FIG. 21 the synchronization code 1202 forframe m+3 is detected next after synchronization code 1201 for frame mwas detected. The synchronization code for frame m+1 should have beendetected, but a synchronization delay of one frame or more from thenormal timing resulted from a sudden increase in the clock frequency dueto an out-of-step PLL, for example.

[0223] The detection result of synchronization code is set to“out-of-step” (10) by the frame synchronization step 301 in this case,and the lowest two bits of the result information for detection ofsynchronization code 1206 for frame m+3 are set by the resultinformation for detection of synchronization code generating step 302 to10.

[0224] Because the synchronization code 1202 was detected at a timingoffset from the timing predicted from the clock, the framesynchronization step 301 corrects synchronization to the timing of thedetected synchronization code 1202.

[0225] Based on frame synchronization by frame synchronization step 301,the modulated frame data 1204 is demodulated by the demodulation step303, resulting in demodulated frame data 1208.

[0226] The adding step 304 then prepends the result information fordetection of synchronization code to each demodulated frame data blockand sends the result to the memory step 305 for writing to memory in theerror correcting circuit block. Because the result information fordetection of synchronization code is added to each demodulated framedata block, correlation to the detection result of synchronization codefor the demodulated frame data is also simple.

[0227] Demodulated frame data for which the result information fordetection of synchronization code is set to “correct synchronization”can therefore be easily identified.

[0228]FIG. 22 shows storing the transferred demodulated frame datahaving the result information for detection of synchronization codeprepended to the beginning thereof as shown in FIG. 21. As shown in FIG.22 the result information for detection of synchronization code and thedemodulated frame data are stored to separate areas in memory. Note thatthe demodulated frame data and corresponding result information fordetection of synchronization code are stored linked to each other.

[0229] The result information for detection of synchronization code anddemodulated frame data are stored by frame number to a specific addressin each memory area. For example, the lowest two bits of resultinformation for detection of synchronization code 1302 for frame m+3 are10, and the data is stored to the address specified for frame m+3. Thedemodulated frame data 1303 for frame m+3 is likewise stored to theaddress specified for frame m+3.

[0230] The result information for detection of synchronization code anddemodulated frame data for frames m+1 and m+2 were not received, and aretherefore skipped and not stored. This can be easily accomplished byreferencing the frame number stored to the high bits of the resultinformation for detection of synchronization code.

[0231] When frame data is thus skipped and not stored, the code (01)indicating that the synchronization code was not detected is preferablystored to the skipped result information for detection ofsynchronization code. In this example, the result information fordetection of synchronization code for frames m+1 and m+2 would thereforebe stored with a type value of 01. Thus storing the undetected code (01)enables generating a erasure pointer to the skipped demodulated framedata as further described below.

[0232] A case in which a synchronization delay of one frame or moreoccurs immediately after a frame is detected normally is describedabove. It will be noted that the same process can be applied when thesynchronization code is undetected for plural consecutive frames, aframe synchronization code is then detected, the clock is reset to thisframe to predict the timing of the next synchronization code, and thereis then a shift of one frame or more between the next-detectedsynchronization code and the timing at which that synchronization codewas predicted.

EXAMPLE 6

[0233]FIG. 23 and FIG. 24 show a fourth example in which synchronizationcorrection is needed because the synchronization code is detected at atime different from that predicted from the timing of the precedingsynchronization code. Conversely to the fifth example described above, asynchronization advance of one whole frame or more is corrected in thisexample.

[0234]FIG. 23A shows the data format of the playback signal input inframe synchronization step 301, and FIG. 23B shows the data format ofthe demodulated frame data and result information for detection ofsynchronization code passed from adding step 304 to memory step 305.

[0235] In the example shown in FIG. 23 synchronization code 1402 forframe m is detected again after synchronization code 1401 for frame mwas detected. While the synchronization code for frame m+1 should havebeen detected here, this case can be processed in the same way as whenthe first frame m synchronization code 1401 is falsely detected, or whenthere is a shift of one frame or more between a newly detectedsynchronization code and where that synchronization code is predicted bycounting the clock from the frame where a synchronization code isfinally detected after the synchronization code is undetected for pluralconsecutive frames.

[0236] The detection result of synchronization code is set to“out-of-step” (10) by the frame synchronization step 301 in this case,and the lowest two bits of the result information for detection ofsynchronization code 1406 for frame m are set by the result informationfor detection of synchronization code generating step 302 to 10.

[0237] Because the synchronization code 1402 was detected at a timingoffset from the timing predicted from the clock, the framesynchronization step 301 corrects synchronization to the timing of thedetected synchronization code 1402.

[0238] Based on frame synchronization by frame synchronization step 301,the modulated frame data 1404 is demodulated by the demodulation step303, resulting in demodulated frame data 1408.

[0239] The adding step 304 then prepends the result information fordetection of synchronization code to each demodulated frame data blockand sends the result to the memory step 305 for writing to memory in theerror correcting circuit block. Because the result information fordetection of synchronization code is added to each demodulated framedata block, correlation to the detection result of synchronization codefor the demodulated frame data is also simple.

[0240] Demodulated frame data for which the result information fordetection of synchronization code is set to “out-of-step” can thereforebe easily identified.

[0241] Note that the data for frame m is sent twice in this example.

[0242]FIG. 24 shows storing the transferred demodulated frame datahaving the result information for detection of synchronization codeprepended to the beginning thereof as shown in FIG. 23. As shown in FIG.24 the result information for detection of synchronization code and thedemodulated frame data are stored to separate areas in memory. Note thatthe demodulated frame data and corresponding result information fordetection of synchronization code are stored linked to each other.

[0243] The result information for detection of synchronization code anddemodulated frame data are stored by frame number to a specific addressin each memory area. For example, the lowest two bits of resultinformation for detection of synchronization code 1502 for frame m are10, and the data is stored to the address specified for frame m. Thedemodulated frame data 1503 for frame m is likewise stored to theaddress specified for frame m.

[0244] The result information for detection of synchronization code anddemodulated frame data for frame m are transferred twice in thisexample, and the data that is transferred and written first is thenoverwritten by the second set of data. Similarly to skipping an addressblock, this overwrite operation can be easily accomplished byreferencing the frame number stored to the high bits of the resultinformation for detection of synchronization code.

[0245] Synchronization code detection and synchronization corrected aredescribed in detail above with reference to FIG. 13 to FIG. 24. Furtherpreferably, however, a window for limiting the synchronization codedetection range is provided with the size of the window variableaccording to the continuity of synchronization code detection andnon-detection, thereby providing greater robustness to falsesynchronization code detection.

[0246] The erasure pointer generating step 306 is described in detailnext with reference to FIG. 25. FIG. 25 shows generating a erasurepointer from result information for detection of synchronization codestored in memory to demodulated frame data stored in a different memoryarea. FIG. 25A shows the result information for detection ofsynchronization code, and FIG. 25B shows the demodulated frame data forthe sector error correcting code, which as described above withreference to FIG. 10A is 8 bytes wide and 128 data bytes plus 16 paritybytes long. The erasure pointers are generated by frame data unit, i.e.,in 8-byte wide rows as shown in FIG. 25.

[0247] As also described above, the result information for detection ofsynchronization code takes one of three values: 00 denoting normalsynchronization code detection, 01 denoting the signal is not detected,and 10 denoting out-of-step synchronization.

[0248] (a) If the result is 00, normal detection, a erasure pointer isnot generated for the corresponding demodulated frame data.

[0249] (b) If the result is 01, undetected (1606), the demodulated framedata 1608 for that frame is considered unreliable becausesynchronization was based only on the clock count from the previouslydetected synchronization code. A erasure pointer 1604 to thisdemodulated frame data 1608 is therefore generated.

[0250] (c) If the result is 10, out-of-step (1607), the demodulatedframe data 1609 for the preceding frame is considered unreliable becausesynchronization correction was applied for frame synchronizationdetection. A erasure pointer 1605 to the demodulated frame data 1609 forthe preceding frame is therefore generated.

[0251] Erasure correction is then applied to the code error positionsindicated in the column direction by the erasure pointers. Erasurecorrection can improve by up to twice the number of corrections per codeunit.

[0252] It should be noted that these erasure pointers can be generatedby storing the row number, for example, where the correspondingdemodulated frame data is stored in a register that can be referenced bythe error correcting circuit during erasure error correction.

[0253] The playback method of this second embodiment of the inventiondescribed above can thus execute erasure correction by sending theresult information for detection of synchronization code with thedemodulated frame data to the error correcting circuit block and usingthis to generate erasure pointers as appropriate. High reliability dataplayback can therefore be achieved.

[0254] Embodiment 3

[0255] This third embodiment of the invention is a playback apparatusfeaturing a circuit design corresponding to the playback methoddescribed in the second embodiment above. FIG. 26 is a block diagram ofthis playback apparatus comprising a demodulation circuit block 1701 anderror correction circuit block 1702. The demodulation circuit block 1701has a frame synchronization circuit 1703, result information fordetection of synchronization code generating circuit 1705, demodulationcircuit 1704, and adding circuit 1706 for the detection result ofsynchronization code. The error correction circuit block 1702 has anerror correction circuit 1710 and erasure pointer generating circuit1709, and also uses external memory 1708 in the error correctingprocess.

[0256] Operation of this playback apparatus is described next.

[0257] (a) The playback signal 1713 from the optical disc is input toframe synchronization circuit 1703.

[0258] (b) The frame synchronization circuit 1703 detects thesynchronization code at the beginning of each frame and synchronizes theframe. The detection result of synchronization code 1715 resulting fromframe synchronization is then sent to the result information fordetection of synchronization code generating circuit 1705. The modulatedframe data 1714 is also sent to the demodulation circuit 1704. Thisframe synchronization circuit 1703 can be easily achieved using meanssuch as a pattern comparison circuit or counter.

[0259] (c) The demodulation circuit 1704 demodulates the modulated framedata 1714 and outputs demodulated frame data 1716. This demodulationcircuit 1704 is a demodulation circuit for (8,16) modulation as knownfrom the literature.

[0260] (d) The result information for detection of synchronization codegenerating circuit 1705 codes the detection result of synchronizationcode 1715 according to a known rule. As described above, normalsynchronization code detection is coded 00, signal non-detection iscoded 01, and out-of-step synchronization is coded 10. The resultinformation for detection of synchronization code generating circuit1705 combines these result codes with the low six bits of the framenumber to product the one-byte result information for detection ofsynchronization code 1717. The result information for detection ofsynchronization code generating circuit 1705 can be achieved with logiccircuits, for example.

[0261] (e) The adding circuit 1706 then prepends the result informationfor detection of synchronization code 1717 to the beginning of thedemodulated frame data 1716 for each frame and sends the result to errorcorrection circuit block 1702. The adding circuit 1706 also sends acontrol signal 1721 for separating the result information for detectionof synchronization code and the demodulated frame data with the transferdata 1719. The adding circuit 1706 could be a selector, for example.

[0262] (f) The splitting circuit 1707 then separates the transferredresult information for detection of synchronization code and demodulatedframe data using the control signal 1721. The separated resultinformation for detection of synchronization code and demodulated framedata are then passed through bus control circuit 1711 and stored toseparate areas in memory 1708. The splitting circuit 1707 can be easilyachieved using two discrete address generating circuits, detaileddescription of which is omitted.

[0263] (g) The erasure pointer generating circuit 1709 then generatesany erasure pointers from the result information for detection ofsynchronization code stored to memory 1708, and stores the pointers to aregister than the error correction circuit 1710 can reference. Thiserasure pointer generating circuit 1709 could be a microprocessor.

[0264] (h) The error correction circuit 1710 applies erasure correctionusing the erasure pointers to the error correcting code from thedemodulated frame data stored in memory. This error correction circuit1710 could be a Reed-Solomon error correcting circuit as known from theliterature.

[0265] (i) The interface control circuit 1712 then sends theerror-corrected playback data 1720 stored in memory 1708 to an MPEGdecoding circuit, for example. This interface control circuit 1712 couldbe an interface circuit to an ATAPI, SCSI, or other protocol controlcircuit.

[0266] (j) The bus control circuit 1711 controls the internal bus 1718and reading/writing memory 1808.

[0267] The playback apparatus according to this third embodiment of theinvention as described above thus sends the result information fordetection of synchronization code with the demodulated frame data to theerror correcting circuit block, and generates erasure pointers therefromto enable erasure correction. High reliability data playback can therebybe achieved.

[0268] Frame synchronization, result information for detection ofsynchronization code, and erasure pointer generation are the same as inthe second embodiment above, and further description thereof is thusomitted.

[0269] Embodiment 4

[0270] An optical disc drive comprising the playback control circuit1814 according to the above third embodiment for playing content from anoptical disc is described below according to a fourth embodiment of theinvention. FIG. 27 is a block diagram of an optical disc drive forreproducing data from an optical disc 1801 storing compressed imagedata. In addition to the playback control circuit 1814 according to thethird embodiment above, this optical disc drive has an optical head 1802comprising a semiconductor laser and other optical elements, a playbackcircuit 1803 for digitizing an analog playback signal and generating adigital playback signal, an MPEG decoding circuit 1807 for decompressingMPEG-compressed data, a DA conversion circuit 1808, and a control CPU1809 for controlling overall operation of the optical disc drive. Theplayback control circuit 1814 includes a demodulation circuit block1804, error correction circuit block 1805, and memory 1806.

[0271] Operation of this optical disc drive is described next.

[0272] A laser beam from the semiconductor laser of the optical head1802 is reflected to the optical head 1802 as reflected light modulatedby the pits or dots formed on the recording surface of the optical disc1801. This modulated reflected light is then converted to an electronicsignal by a photoelectric element, and input to the playback circuit1803 as an analog playback signal 1810. The playback circuit 1803converts this analog signal to a digital signal, and outputs theresulting digital playback signal to the playback control circuit 1814.

[0273] As described in the third embodiment above, the playback controlcircuit 1814 applies frame synchronization, demodulation, and erasurecorrection using the erasure pointers generated from result informationfor detection of synchronization code. These operations are described indetail in the third embodiment above, and further description istherefore omitted here.

[0274] The error-corrected playback data 1811 is then decoded by theMPEG decoding circuit 1807. The decompressed playback data 1812 is thenanalog converted by the DA conversion circuit 1808, and sent to a TV orother presentation system as AV signal 1813.

[0275] Operation of this optical disc drive is controlled by the controlCPU 1809. It should be noted that control signals and servo circuits forfocusing and tracking are not shown in the figure.

[0276] The optical disc drive according to this fourth embodiment of theinvention adds result information for detection of synchronization codeto the corresponding demodulated frame data, sends the result to theerror correcting circuit block, and thus generates erasure pointers foridentifying specific demodulated frame data to which erasure correctionis then applied. Data can therefore be reproduced with high reliability.

[0277] Although the present invention has been described in connectionwith the preferred embodiments thereof with reference to theaccompanying drawings, it is to be noted that various changes andmodifications will be apparent to those skilled in the art. Such changesand modifications are to be understood as included within the scope ofthe present invention as defined by the appended claims, unless theydepart therefrom.

[0278] The present disclosure relates to subject matter contained inJapanese Patent Application Nos. 2002-326492, filed on Nov. 11, 2002,and 2002-328054, filed on Nov. 12, 2002, the contents of both are hereinexpressly incorporated by reference in their entireties.

What is claimed is:
 1. A playback method for a recording medium to whichdata is recorded in block units containing multiple fixed-length framestogether with block address information, the playback method comprisingsteps of: acquiring the data and the block address information from therecording medium; predicting the recording position of each frame in ablock from the acquired block address information; synchronizing to theframe level based on the acquired data; determining the memory addressfor storing the data acquired based on the predicted recording position;and storing the acquired data at the determined memory address.
 2. Aplayback method for a recording medium according to claim 1, furthercomprising steps of: determining whether synchronization at the dataframe unit level has been established; and detecting whethersynchronization at the frame unit has been restored if framesynchronization goes out-of-step; wherein when recovery of framesynchronization is detected, the memory address to which data is storedis determined based on the predicted frame recording position.
 3. Aplayback method for a recording medium according to claim 1, wherein thedata memory address in memory is determined with the frame as thesmallest recordable unit.
 4. A playback method for a recording mediumaccording to claim 1, wherein block address information is recorded tothe recording medium in a format different from the data recordingformat.
 5. A playback method for a recording medium according to claim1, further comprising steps of: generating a result information fordetection of synchronization code coded at the frame unit levelaccording to specific rules; demodulating the data in each frame todemodulated frame data; and adding to each demodulated frame data blockthe result information for detection of synchronization code correlatedto each frame.
 6. A playback method for a recording medium according toclaim 1, further comprising a step of synchronizing at the frame unitlevel based on the acquired address information.
 7. A playback controlcircuit for a recording medium to which data is recorded in block unitscontaining multiple fixed-length frames together with block addressinformation, comprising: signal reading means for acquiring the data andthe block address information from the recording medium; a recordingaddress predicting means for predicting the recording position of eachframe in a block from the acquired block address information;synchronization means for synchronizing to the frame level based on theacquired data; memory for storing the data; and control means fordetermining the memory address for storing data based on the predictedrecording position.
 8. A playback control circuit according to claim 7,further comprising a synchronization detection means for determiningwhether synchronization at the data frame unit level has beenestablished, and detecting whether synchronization at the frame unit hasbeen restored if frame synchronization goes out-of-step; wherein thecontrol means determines the memory address to which data is storedbased on the recording position predicted by the recording addresspredicting means when the synchronization detection means detectsrecovery of frame synchronization.
 9. A playback control circuitaccording to claim 7, wherein the data memory address in memory isdetermined with the frame as the smallest recordable unit.
 10. Aplayback apparatus for a recording medium to which data is recorded inblock units containing multiple fixed-length frames together with blockaddress information, comprising the playback control circuit accordingto claim
 7. 11. A playback method for reproducing data from a recordingmedium to which is recorded modulated frame data and a specificsynchronization code prepended to the beginning of the modulated framedata, the modulated frame data being error correction coded datasegmented into multiple frame data blocks of a specific length and thenmodulated, the playback method comprising steps of: acquiring signalsfrom the recording medium; acquiring a detection result ofsynchronization code by detecting frame synchronization codes from theacquired signals; correcting frame synchronization based on the resultfor detection of acquired synchronization code; generating a resultinformation for detection of synchronization code coded according tospecific rules from the detection result of synchronization code;demodulating the modulated frame data for each frame and generatingdemodulated frame data; and adding the result information for detectionof synchronization code for each frame to the corresponding demodulatedframe data.
 12. A playback method according to claim 11, furthercomprising: a erasure pointer generating step for generating a erasurepointer for erasure correction based on the demodulated frame data usingthe corresponding result information for detection of synchronizationcode; and an error correcting step for erasure correcting errorcorrecting code from multiple demodulated frame data blocks using theerasure pointers for the demodulated frame data.
 13. A playback methodaccording to claim 11, further comprising: a memory step for storing theresult information for detection of synchronization code andcorresponding demodulated frame data in different memory areas with aknown correlation therebetween.
 14. A playback method according to claim11, wherein the result information for detection of synchronization codeis coded to differentiate between at least the three detection resultsof “normal detection” when the synchronization code is detectednormally, “undetected” when the synchronization code is not detected,and “out-of-step synchronization” when a next synchronization code isdetected at a timing offset from a timing predicted from the timing ofthe detection result for the previously detected synchronization code.15. A playback method according to claim 11, wherein when the framesynchronization step corrects synchronization delay in which a newsynchronization code is detected earlier than the timing predicted fromthe timing of the detection result of the previously detectedsynchronization code, and the synchronization delay is less than oneframe, the memory step corrects the memory address of the frame dataimmediately after synchronization delay correction to an address derivedby skipping an amount equivalent to the synchronization delaycorrection, and stores the frame data to the corrected address.
 16. Aplayback method according to claim 15, wherein when the framesynchronization step corrects synchronization delay in which a newsynchronization code is detected earlier than the timing predicted fromthe timing of the previously detected synchronization code, and thesynchronization delay is greater than or equal to one frame, the memorystep corrects the memory address of the result information for detectionof synchronization code and frame data immediately after synchronizationdelay correction to an address shifted equivalently to the correctionfor the synchronization delay, and then stores the data to the correctedaddress; and the erasure pointer generating step determines that resultinformation for detection of synchronization code that is skipped andnot stored to memory was undetected, and generates a erasure pointerthereto.
 17. A playback control circuit for reproducing data from arecording medium to which is recorded modulated frame data and aspecific synchronization code prepended to the beginning of themodulated frame data, the modulated frame data being error correctioncoded data segmented into multiple frame data blocks of a specificlength and then modulated, the playback control circuit comprising: aframe synchronization means for correcting frame synchronization basedon a detection result of synchronization code acquired by detectingframe synchronization codes from playback signals acquired from therecording medium; a generating means for generating a result informationfor detection of synchronization code coded according to specific rulesfrom the detection result of synchronization code; a demodulation meansfor demodulating the modulated frame data for each frame and generatingdemodulated frame data; an adding means for prepending the resultinformation for detection of synchronization code for a frame to thebeginning of the demodulated frame data; memory for storing the resultinformation for detection of synchronization code and demodulated framedata; and memory control means for storing the result information fordetection of synchronization code and demodulated frame data to memory.18. A playback control circuit according to claim 17, furthercomprising: erasure pointer generating means for generating a erasurepointer for erasure correction using the result information fordetection of synchronization code; and an error correcting means forerasure correcting error correcting code composed from demodulated framedata using the erasure pointers.
 19. A playback control circuitaccording to claim 17, wherein the memory control means stores theresult information for detection of synchronization code and demodulatedframe data to different memory areas.
 20. A playback control circuitaccording to claim 17, wherein the result information for detection ofsynchronization code is coded to differentiate between at least thethree detection results of “normal detection” when the synchronizationcode is detected normally, “undetected” when the synchronization code isnot detected, and “out-of-step synchronization” when a nextsynchronization code is detected at a timing offset from a timingpredicted from the timing of the detection result for the previouslydetected synchronization code.
 21. A playback control circuit accordingto claim 17, wherein when the frame synchronization means correctssynchronization delay in which a new synchronization code is detectedearlier than the timing predicted from the timing of the previouslydetected synchronization code, and the synchronization delay is lessthan one frame, the memory control means corrects the memory address ofthe frame data immediately after synchronization delay correction to anaddress derived by skipping an amount equivalent to the synchronizationdelay correction, and stores the frame data to the corrected address.22. A playback control circuit according to claim 21, wherein when theframe synchronization means corrects synchronization delay in which anew synchronization code is detected earlier than the timing predictedfrom the timing of the previously detected synchronization code, and thesynchronization delay is greater than or equal to one frame, the memorycontrol means corrects the memory address of the result information fordetection of synchronization code and frame data immediately aftersynchronization delay correction to an address shifted equivalently tothe correction for synchronization delay, and then stores the frame datato the corrected address; and the erasure pointer generating meansdetermines that result information for detection of synchronization codecorrespond to a frame that is skipped and not stored to memory wasundetected, and generates a erasure pointer thereto.
 23. A playbackapparatus for reproducing data from a recording medium to which isrecorded modulated frame data and a specific synchronization codeprepended to the beginning of the modulated frame data, the modulatedframe data being error correction coded data segmented into multipleframe data blocks of a specific length and then modulated, the playbackapparatus comprising the playback control circuit according to claim 17.